This invention relates to a memory device, and more particularly, to a memory device utilized for storing phone numbers comprising an IC circuit.
FIG. 1 illustrates a circuit diagram of a memory device for phone numbers according to the prior art. The memory device comprises a memory array 100 having a plurality of memory cells 10 arranged as a matrix; a Y address decoder 30 which selects Y addresses of the memory array 100; an X address decoder 50 which selects X addresses of the memory array 100 in order to read out data to bus lines 40; data lines 60 through which data are read out from memory cells 10 selected by the Y address decoder 30; switches 70 which precharge the data lines 60; and switches 80 connected between the data lines 60 and the bus lines 40, which ON/OFF operation is controlled by the X address decoder 50. Since a unit phone number is stored in memory cells along a row of the matrix, a selection of a Y address corresponds to selection of a unit phone number.
FIGS. 2 and 3 are circuit diagrams showing examples of the prior art memory cell 10. A selecting operation effected by the Y address decoder 30 usually consists of a write operation and a readout operation, wherein each operation is executed separately.
In the memory cell illustrated in FIG. 2, a data memory part comprises of inverters 11 and 12, and a switch for writing and reading out data comprises transistors 13, 14, 15 and 16. A data line 60 is connected to a precharge switch 70 and to another data line 60' through an inverter 17.
In the memory cell illustrated in FIG. 3, a data memory part comprises an inverter 11 and a clocked inverter 18 controlled by a signal W which is an inverse signal of a write signal W, and a switch for writing and reading out data, the switch comprising transistors 13, 14 and a switch 19 controlled by the write signal W. In both the circuits described above, a data is stored in a line 20 in the data memorizing part.
The operation of the memory device illustrated in FIG. 1 is as follows. Firstly, an operation of reading out data is explained. When a Y address is selected by the Y address decoder 30, data in the memory cells 10 along the row corresponding to the selected address are outputted to data lines 60. Since one digit of a phone number is represented by a number of bits in a memory device, the corresponding number of bus lines is provided. Therefore a data having the number of bits is outputted simultaneously.
A unit phone number data is sequentially outputted to the bus lines 40, digit after digit, from the upper order digits to the lower order digits when X addresses are successively selected. Therefore all the digits constituting the unit phone number are successively obtained on bus lines 40.
In the case of the memory device shown in FIG. 1, one digit consists of 5 data bits. When the data in memory cells 10 are to be outputted to the data lines 60, the data lines 60 must be precharged to a high level. This precharge is made by turning on the precharge switch 70 at a predetermined timing so that the source voltage V.sub.DD is applied to the data lines.
The precharge is needed because of the following reason. When the memory cell 10 holds a high level data (hereinafter merely referred to as "H"), that is, the line 20 holds "H", the data "H" cannot be read out from the memory part to the data line 60 if it is not precharged, because the transistor 13 is turned off. If the data line 60 is precharged by turning on the precharge switch 70, the data "H" can be obtained on the data line 60, thus reading out "H". On the other hand, when the memory cell 10 holds a low level data (hereinafter merely referred to as "L"), that is, the line 20 holds "L", the data "L" can be read out from the memory part to the data line 60 through the transistors 13 and 14 because these transistors are turned on. Though the precharge switch 70 is still turned on, the data "L" can be obtained on the data line 60 because the sum of the resistance values of transistors 13 and 14 in the ON condition is set to become much smaller than the resistance value of the precharge switch 70 in the ON condition.
Secondly, the operation of writing data will now be described. A data for each digit of a phone number is successively transmitted to the bus lines 40, digit after digit, from the upper order digit to the lower order digit at a predetermined timing. The transmitted data for each digit is stored in five memory cells selected by the Y address decoder 30 and the X address decoder 50. Before this storing operation, the voltage level in each data line 60 must be set to the same level as in the corresponding memory cell along the row selected. This reason is described as follows.
When a storing operation is executed, all the transistors 15, 16 or all the switches 19 in memory cells along the row selected by the Y address decoder are turned on so that all data lines 60 are connected to memory cells along the row selected. During this storing operation, although memory cells located in the row selected by the Y address decoder and in the columns selected by the X address decoder are refreshed with the data in the data lines 60, the other memory cells located in the same row should still hold their former data without regard to the data in the data lines 60. This is the reason why the voltage level in each data line 60 must be the same as that in the corresponding memory cell. In conclusion, before every write operation, an extra readout operation is needed so that the former data in the memory cells along the selected row are outputted to the data lines 60. Otherwise some data in the memory cells would be changed unexpectedly.
As described above, a unit phone number comprises a plurality of digits, and each digit consists of a number of bits (in this example, five bits). Therefore, in a readout operation, the X address decoder 50 must select each group of five adjacent bit addresses succeedingly one after another so as to output a series of one digit data to the bus lines 40. In the memory cell 10 shown in FIGS. 2 or 3, the data lines 60 must be precharged by turning on the precharge switches 70 every time when the address shift is made by the X address decoder 50.
This frequent precharge causes the following problems. That is, as far as a memory cell 10 outputting "L" is concerned, an electric current flows from a power source V.sub.DD to a power source V.sub.SS through the precharge switches 70 and the transistors 13 and 14 during all the precharging time. This wastes electric power, especially in a device having a lot of memory cells.
Another problem of the prior art described above is concerned with the drive ability of memory cells. Because of parasitic capacitance of the bus lines 40 etc., a memory cell must have sufficient drive ability to transmit output data to the bus lines 40. In order to provide sufficient drive ability, each semiconductor device which constitutes a memory cell must be designed to have a large dimension, and therefore, integration of memory cells is prevented. Besides, the voltage of a power source must be set relatively high.
Additional problem is concerned with operating speed. As described above, before every write operation, an extra readout operation must be taken. This procedure delays the operation speed.